1. Field of the Invention
The invention relates to a method of synchronizing the exchange of data between hardware and software via a buffer containing both data and control information, and more particularly where the CPU is not required to synchronize the data exchange between hardware and software thereby saving clock cycles.
2. Description of the Related Art
Typically, the hardware (HW) in a System-On-Chip (SOC) design operates in the following fashion, as shown in FIG. 1, a flowchart of the prior art.
1. Block 10: the hardware stays in the idle state, waiting for instructions from the software (SW, i.e. CPU).
2. Block 11: the CPU programs the registers in the hardware module to set up various control information.
3. Block 12: after register programming is finished, the CPU enables the hardware (Block 13).
4. Block 14: the hardware starts performing the desired operations as specified by the control parameters.
5. Block 15: after the operations are finished, the hardware raises an interrupt to notify the CPU (Block 16) and goes back to the idle state (Block 10), waiting for the HW interrupt. And repeating the sequence:
6. Block 11: upon receiving the HW interrupt, the CPU moves on to schedule the next HW task, starting with new register programming.
The above scheme often results in frequent and inefficient HW/SW communications. For example, in order to perform a long series of operations, each of which may require a different set of control parameters, the CPU needs to baby-sit the HW, feeding a new set of register values upon completion of the previous operation. The CPU in SOC designs often functions in the multi-tasking mode, such as babysitting multiple hardware modules and/or performing its own computations. As a result, it may not be able to respond to the HW interrupt in time. Precious HW clock cycles are thus wasted on waiting for further instructions from the CPU.
For encoding, the CPU programs the registers inside the MPEG encoder to specify the encoding parameters. The MPEG encoder starts encoding and stores encoded video data into either DRAM or an internal buffer (not shown). The MPEG encoder further sends interrupts periodically to the CPU, so that the CPU can read encoded data from the MPEG encoder.
For decoding, the CPU programs the registers inside the MPEG decoder to specify the decoding parameters. The CPU starts decoding and stores decoded video data into either DRAM or the above mentioned buffer inside the MPEG decoder. The CPU then programs the MPEG decoder to start decoding.
The HW/SW synchronization becomes an even more important issue when HW and SW collaborate to work on the same set of data in order to finish one common task. For example, for MPEG (Moving Pictures Expert Group) decoding, the SW may be responsible for bit stream parsing and variable-length decoding, while the HW performs the dequantization (DQ), inverse discrete cosine transformation (IDCT), and motion compensation (MC). Both the data (i.e. IDCT coefficients) and the associated control information (e.g. motion vectors and quantization parameters) are frequently passed between SW and HW. Depending on the SOC architecture, the HW and the SW may not be operating at the same speed, but without an efficient HW and SW interface for exchanging both the data and the control information, the HW and the CPU are forced to operate in a lock-step way.
Prior art U.S. Patents which somewhat address synchronization are:
U.S. Pat. No. 6,775,734 (Chang) discloses a method and system for providing a memory access method using a system management interrupt. When the CPU receives a system management interrupt signal, the signal starts operating in the system management mode and the CPU executes a system management interrupt handler routine. The computer system comprises a CPU, a chipset and a memory unit.
U.S. Pat. No. 6,867,781 (Van Hook et al.) provides for the synchronizing of a graphics pipeline with an external actor such as, e.g., a graphics command producer. A token including a variable data message is inserted into a graphics command sent to a graphics pipeline. At a predetermined point in the pipeline, the token is captured and a signal is generated indicating a token has arrived.
In the method of the prior art, synchronization between encoding and decoding parameters (or control information) and video data is time consuming and inefficient. Therefore precious computation resources are not put to optimal use. What is required is self-synchronization of software and hardware, where data and associated control information are passed between them. Accordingly, a new approach is offered for efficient data/control information transfer.